A field-programmable gate array (FPGA) is an LSI includes logic gates of a lookup table (LUT) base and a switch which connects the gates. The FPGA rewrites memory information which controls the LUT and the switch, which enables the construction of an arbitrary circuit. According to the FPGA, a user can rewrite a desirable circuit after the shipping of chips, and hence it is possible to shorten a development period of time for manufacturing the chips.
A memory which controls the on/off state of the switch of the FPGA is called a configuration memory, and an SRAM cell is mainly used. On the other hand, the switch is often used as a multiplexer. In this case, two types of a positive signal and an inversion signal are required for the control of the switch. Consequently, the SRAM cell which can take out the positive signal and the inversion signal in parallel is suitable for this use application.
However, the SRAM cell consists of six transistors, as is well known, and hence its area is large. Moreover, the SRAM cell is a volatile memory from which data disappears when the power is removed. Therefore, after the power is restored, it is necessary to reread the memory data.
Therefore, nonvolatile configuration memories have been suggested.
For example, a nonvolatile configuration memory consisting of two transistors including floating gates is known. According to this memory, it is unnecessary to reread the memory data after the power is restored. Moreover, the memory cell consists of two transistors, and hence the area thereof can be advantageously restrained.
However, when a high signal is output from the memory cell, the output level does not rise to the supply potential. Therefore, the switch controlled by this output cannot be sufficiently turned on. Consequently, there is a problem that power consumption of a logic circuit connected to a latter part of the switch becomes large.
Moreover, this memory cell outputs the positive signal only. Therefore, when this cell is used as the configuration memory of the multiplexer, an inverter for generating the inversion signal is required in addition to the memory cell. That is, according to this technology, the memory cell requires two transistors and further requires two transistors for generating the inversion signal, and consequently, four transistors in total are required. Therefore, sufficient area reduction cannot be achieved.
On the other hand, there is known a nonvolatile configuration memory in which an N-channel MOS transistor for driving in an SRAM cell is replaced with a nonvolatile memory cell (a transistor including a floating gate). According to this memory, a high output level rises to the supply potential, which eliminates the problem of increased power requirements of the logic circuit connected to the latter part of the switch.
However, this memory cell consists of six transistors, and hence to the goal of decreasing cell area remains unachieved. Moreover, in writing to the transistor including the floating gate, it is necessary to apply a high potential for writing to the gate electrode of the transistor. Consequently, an N-channel MOS transistor for access in the SRAM cell has to be provided with a high withstand pressure, and an area of the transistor becomes large.
Furthermore, the gate electrode of a P-channel MOS transistor for loading in the SRAM cell is connected to the gate electrode of the transistor including the floating gate in the SRAM cell. Consequently, the P-channel MOS transistor for loading has also to be provided with the high withstand pressure so that the transistor is not broken by the high potential for writing, and hence the area of the transistor becomes large.